26 publications
* Corresponding author(s)
IEEE/ACM International Symposium on Microarchitecture (MICRO) Top-Tier
Non-Speculative Redundant Load Elimination
IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Major
Compiler and System Optimizations for Gem5 Simulator
[Best Paper Nomination]
Read publication ↗IEEE/ACM International Symposium on Microarchitecture (MICRO) Top-Tier
Re-architecting End-host Networking with CXL: Coherence, Memory, and Offloading
Read publication ↗IEIE International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC)
DART: Dynamic Resource-Aware Tiling for Multi-PIM Architectures
IEEE Computer Architecture Letters (CAL) SCIE
REDIT: Redirection-Enabled Memory-Side Directory Architecture for CXL Memory Fabric
Read publication ↗IEEE Computer Architecture Letters (CAL) SCIE
Time Series Machine Learning Models for Precise SSD Access Latency Prediction
Read publication ↗ACM/IEEE International Symposium on Computer Architecture (ISCA) Top-Tier
A4: Microarchitecture-Aware LLC Management for Datacenter Servers with Emerging I/O Devices
Read publication ↗ACM/IEEE International Symposium on Computer Architecture (ISCA) Top-Tier
UPP: Universal Predicate Pushdown to Smart Storage
Read publication ↗IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS) Major
Intel® In-Memory Analytics Accelerator: Performance Characterization and Guidelines
[Best Paper Honorable Mention | Distinguished Artifact Award]
Read publication ↗정보과학회 학회지, 제 43권, 제 4호, pp.29-36
최신 범용 프로세서 연구 동향
IEEE International Symposium on High-Performance Computer Architecture (HPCA) Top-Tier
Warped-Compaction: Maximizing GPU Register File Bandwidth Utilization via Operand Compaction
Read publication ↗IEEE International Symposium on High-Performance Computer Architecture (HPCA) Top-Tier
Marching Page Walks: Batching and Concurrent Page Table Walks for Enhancing GPU Throughput
Read publication ↗IEEE/ACM International Symposium on Microarchitecture (MICRO) Top-Tier
Demystifying a CXL Type-2 Device: A Heterogeneous Cooperative Computing Perspective
Read publication ↗ACM/IEEE International Symposium on Computer Architecture (ISCA) Top-Tier
HAL: Hardware-assisted Load Balancing for Energy-efficient SNIC-Host Cooperative Computing
Read publication ↗ACM/IEEE International Symposium on Computer Architecture (ISCA) Top-Tier
Intel Accelerators Ecosystem: An SoC-Oriented Perspective : Industry Product
Read publication ↗IEEE Embedded Systems Letters SCIE
Triple-A: Early Operand Collector Allocation for Maximizing GPU Register Bank Utilization
Read publication ↗ACM Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) Top-Tier
A Quantitative Analysis and Guidelines of Data Streaming Accelerator in Modern Intel Xeon Scalable Processors
Read publication ↗ACM Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS) Top-Tier
TAROT: A CXL SmartNIC-Based Defense Against Multi-bit Errors by Row-Hammer Attacks
Read publication ↗ACM SIGOPS European Conference on Computer Systems (EuroSys) Major
ScaleCache: A Scalable Page Cache for Multiple Solid-State Drives
Read publication ↗International Conference on Electronics, Information, and Communication (ICEIC)
A Multi-DNN Acceleration Architecture for Balanced QoS and Throughput
Journal of Systems Architecture SCIE
A Convertible Neural Processor Supporting Adaptive Quantization for Real-Time Neural Networks
Read publication ↗IEEE/ACM International Symposium on Microarchitecture (MICRO) Top-Tier
Demystifying CXL Memory with Genuine CXL-Ready Systems and Devices
Read publication ↗ACM International Conference on Parallel Architectures And Compilation Techniques (PACT) Top-Tier
INTERPRET: Inter-Warp Register Reuse for GPU Tensor Core
Read publication ↗IEEE Computer Architecture Letters SCIE
LADIO: Leakage-Aware Direct I/O for I/O-Intensive Workloads
Read publication ↗IEEE Embedded Systems Letters SCIE
CASH-RF: A Compiler-Assisted Hierarchical Register File in GPUs
Read publication ↗IEEE/ACM International Symposium on Microarchitecture (MICRO) Top-Tier
Reconstructing Out-of-Order Issue Queue
Read publication ↗IEEE International Symposium on High-Performance Computer Architecture (HPCA) Top-Tier
CASINO Core Microarchitecture: Generating Out-of-Order Schedules Using Cascaded In-Order Scheduling Windows
Read publication ↗IEEE Transactions on Computers SCIE
OverCome: Coarse-Grained Instruction Commit with Handover Register Renaming
Read publication ↗IEEE International Conference on Consumer Electronics Asia (ICCE-ASIA)
Constructing Resilient Region in Dynamic Optimization Systems via Dynamic Adjustment of Bias Thresholds
International SoC Design Conference (ISOCC)
Parallel In-Order Execution Architecture for Low-Power Processor
Read publication ↗International Conference on Electronics, Information, and Communication (ICEIC)
Dynamic Warp Scheduler Selection Policy Using Linear Regression for GPUs
Annual Summer Conference of IEIE
Heterogeneous Core Microarchitecture with Functional Unit Gating for High Energy Efficiency
Annual Summer Conference of IEIE
Analyzing Development Trends and Performance/Power Characteristics of Multi-Core Processors
Annual Fall Conference of KIPS
Exploiting Back-End Fusion in Multi-Core Processors
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